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iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
FEATURES o Configurable quadrature 3-channel binary counter of 16, 24, 32 and 48 bit (TTL, RS422 or LVDS input) o Fast RS422 12 V receiver for differential A/B/Z encoder signal o Count frequency to 40 MHz o Monitoring of A/B phase logic with error message o Evaluation of distance-coded reference marks o Pin-triggered touch-probe function with selectable hi/lo edge sensitivity o Error and warning signal generation o Operation from 3.3 V to 5 V o Configuration via bus capable SPI and BiSS Interface o Two actuator output signals o Default operation mode permits plug & play without programming o 3 Channel 16 bit counting (TTL: A/B) o 2 Channel 16, 24 or 16+32 bit counting (TTL: AP/AN/BP, BN/CP/CN) o 1 Channel 16, 24, 32 or 48 bit counting (TTL: AP/AN/BP or RS422, LVDS: A/B/C differential)
APPLICATIONS o PLC interface to linear scales, rotary encoders, digital gauges o Motion control
PACKAGES
TSSOP 20
BLOCK DIAGRAM
VDD RS-422/TTL RECEIVERS AP
MULTIPLEXER
REFERENCE-TO-REFERENCE COUNTER 24 Bit
UPD Register
DATA I/O AND STATUS ERROR REGISTERS NWARN WARNING NERR
+
AN BP
REFCNT REF Register
+
A0 B0 Z0 A1 CNT 0 24 Bit 24 Bit 48 Bit 32 Bit 32 Bit A2 B2 16 Bit 16 Bit 16 Bit CNT 1 24 Bit 16 Bit 16 Bit 16 Bit
CONFIGURABLE COUNTERS CNT 2 16 Bit SPI INTERFACE NCS SCK MISO MOSI ACTUATOR OUTPUT ACT1 ACT0
BN
CP
B1
+
Z1
CN
TOUCH PROBE
SERIAL INTERFACE BiSS C SSI
MA SLI SLO
TPI
iC-MD
TP1
ENTP &
TP2
GND
Copyright (c) 2006, 2010 iC-Haus
http://www.ichaus.com
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
DESCRIPTION iC-MD evaluates incremental encoder signals with A, B and index tracks from up to three encoders. After power-on the iC-MD has all the RAM bits at 0 as default configuration, that means one 24 bit counter configured, and differential inputs. The device can be programmed via the SPI interface or BiSS Interface. The 48 bit counter can be configured as up to three counters with variable counter depths of 16, 24, 32 or 48 bits, but the sum of bits of all the configured counters can not be higher than 48 bits. Some of the possible configurations are 1x48 bit, 2x24 bit, 3x16 bit, 1x32 + 1x16 bit. Each edge of the synchronized encoder signal counts (fourfold edge evaluation). An additional 24bit counter REF counter is used to store the distance (number of pulses) between the first two index pulses after power-on and the distance between every last two index pulses in UPD register. An event at the input pin TPI (configurable as rising, falling or both edges) loads the register TP1 with the actual value of the counter 0, and shift the old value of TP1 in register TP2. This registers can also be loads through the instruction bit TP, via SPI or BiSS (Register communication). Two bidirectional ports are used as error and warning output (low active) and can be pulled down from outside to signals an external error or external warning. This external error and warning are internally latched in the status registers. A set of status registers monitor the status of the counter, TP1, TP2, REF, UPD, power on and external error and warning pins. The BiSS Interface reads out the counter and registers TP1, TP2 and UPD as Sensor data. REF register is read via BiSS register communication.
PACKAGES PIN CONFIGURATION TSSOP20 4.4 mm, lead pitch 0.65 mm PIN FUNCTIONS No. Name Function BiSS/SSI Interface, data output BiSS/SSI Interface, data input BiSS/SSI Interface, clock input Signal Input (CNT0 / CNT0) Signal Input (CNT0 / CNT0) Signal Input (CNT0 / CNT1) Signal Input (CNT1 / CNT1) Signal Input (CNT1 / CNT2) Signal Input (CNT1 / CNT2) Ground Error Message Output (low active) / System Error Message Input 12 NWARN Warning Message Output (low active) / System Warning Message Input 13 MISO SPI Interface, data ouput 14 MOSI SPI Interface, data input 15 SCK SPI Interface, clock input 16 NCS SPI Interface, chip select (low active) 17 VDD 3.0 . . . 5.5 VSupply Voltage 18 ACT0 Actuator Output 0 19 ACT1 Actuator Output 1 20 TPI Touch Probe Input 1 2 3 4 5 6 7 8 9 10 11 SLO SLI MA AP AN BP BN CP CN GND NERR
1 SLO 2 SLI 3 MA 4 AP 5 AN 6 BP 7 BN 8 CP 9 CN 10 GND
20 TPI 19 ACT1 18 ACT0 17 VDD 16 NCS 15 SCK 14 MOSI 13 MISO 12 nWARN 11 nERR
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Voltage at VDD Voltage at MA, SLI, NERR, NWARN, NCS, SCK, MOSI, TPI Current in MA, SLI, NERR, NWARN, NCS, SCK, MOSI, TPI Voltage at AP, AN, BP, BN, CP, CN Current in AP, AN, BP, BN, CP, CN ESD Susceptibilty at all pins Junction Temperature Storage Temperature Range HBM 100 pF discharged through 1.5 k -40 -40 Conditions Min. -0.3 -0.3 -4 -7 -20 Max. 7 7 4 7 20 2 150 150 V V mA V mA kV C C Unit
G001 V() G002 V() G003 I() G004 V() G005 I() G006 Vd() G007 Tj G008 Ts
THERMAL DATA
Item No. T01 Symbol Ta Parameter Operating Ambient Temperature Range Conditions Min. -40 Typ. Max. 125 C Unit
All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-MD RS-422 QUADRATURE
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ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 C, unless otherwise noted. Item No. 001 002 Symbol Parameter Conditions Min. VDD I(VDD) Voltage Supply VDD Supply Current in VDD TTL input configuration, 48 bits counter 10 MHz signal in AP (0 phase) and AN (90 phase), BP, BN, CP and CN to GND Vc()hi = V() - VDD, I() = 1 mA Vc()hi = V() - VDD, I() = 10 mA 0.4 -1.5 3 Typ. Max. 5.5 15 V mA Unit
General
003 004 101 102 103 104 105 106 107 108 109
Vc()hi Vc()lo Vt()hi Vt()lo Vt()hys Ipd() Ipu() fclk(MA) Voc() Ri() fclk(SCK)
Clamp Voltage hi Clamp Voltage lo Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input Pull-down Current at SCK, MOSI, TPI Input Pull-Up Current at NCS, MA Permissible Clock Frequency at MA Pin Open Voltage at SLI Internal Resistance at SLI Permissible Clock Frequency at SCK Pull-Up Current Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Saturation Voltage lo Short-Circuit Current lo Counter Resolution Permissible Count Frequency
1.5 -0.25 2
V V V V V
Digital Inputs: MA, SLI, SCK, MOSI, NCS, TPI VDD = 4.5 . . . 5.5 V VDD = 3 . . . 5.5 V V() = 1 V . . . VDD V() = 0 V . . . VDD - 1 V NBISS = 1 (SSI protocol) NBISS = 0 (BiSS protocol) 42 Referenced to VDD Referenced to GND 70 40 46.5 0.8 0.75 150 2 -75 250 30 -30 75 -2 4 10 51 170 110 10
mV A A MHz MHz %VDD k k MHz
Bidirectional Pins: NWARN, NERR 201 202 203 204 205 206 301 302 303 Ipu() Vt()hi Vt()lo Vt()hys Vs()lo Isc()lo R() fcnt() PHab2 V() = 0 V . . . VDD - 1 V VDD = 4.5 . . . 5.5 V VDD = 3 . . . 5.5 V -750 0.8 0.75 150 I() = 4 mA V() = 0 V . . . VDD 4 250 450 100 48 40 5 13 2.9 2.1 VDDon - VDDoff 35 1.4 Vs()hi = VDD - V(), I() = -4 mA I() = 4 mA V() = 0 . . . VDD V() = 0 . . . VDD -115 100 100 5.3 450 450 -100 -10 2 A V V V mV mV mA bit MHz ns ns V V mV MHz mV mV mA mA
ABZ Counter
Permissible A/B Phase Distance edge A vs. edge B and vice versa TTL=1 TTL=0, LVDS=X Power-On Supply Voltage Power-Down Voltage Power-On Hysteresis Internal Oscillator Frequency Saturation Voltage hi Saturation Voltage lo Short-Circuit Current hi Short-Circuit Current lo
Power-Down Reset and Oscillator 601 602 603 604 701 702 703 704 VDDon VDDoff VDDhys Frq(CLK) Vs()hi Vs()lo Isc()hi Isc()lo
Digital Outputs: SLO, MISO, ACT0, ACT1
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 C, unless otherwise noted. Item No. Symbol Parameter Conditions Min. Typ. Max. Unit
RS-422 Configuration: Differential Inputs AP, AN, BP, BN, CP, CN A01 Vcm() Common Mode Voltage Range TTL = 0, LVDS = 0 VDD = 4.5 . . . 5.5 V VDD = 3 . . . 5.5 V A02 Vd() Differential Input Threshold TTL = 0, LVDS = 0, V() = V(AP) - V(AN) Voltage V() = V(BP) - V(BN) V() = V(CP) - V(CN) A03 Vhys() Differential Input Hysteresis TTL = 0, LVDS = 0, Vhys() = Vth()hi-Vth()lo (guaranteed by design)
0 0 -300
3 1.5 300
V V mV
2.5
10
mV
TTL Configuration: Input AP, AN, BP, BN, CP, CN B01 Vt()hi Input Threshold Voltage hi at TTL = 1, LVDS = 0 AP, AN, BP, BN, CP, CN B02 Vt()lo Input Threshold Voltage lo at TTL = 1, LVDS = 0 AP, AN, BP, BN, CP, CN B03 B04 Vt()hys Rpd() Input Hysteresis at AP, AN, BP, BN, CP, CN Pull-Down Resistor TTL = 1, LVDS = 0 TTL = 1, LVDS = 0
2 0.8 150 35 300 50 65
V V mV k
LVDS Configuration: Differential Inputs AP, AN, BP, BN, CP, CN C01 Vin() Input Voltage Range TTL = 0, LVDS = 1 VDD = 4.5 . . . 5.5 V VDD = 3 . . . 5.5 V C02 Vd() Differential Input Threshold TTL = 0, LVDS = 1 V() = V(AP)-V(AN) Voltage V() = V(BP)-V(BN) V() = V(CP)-V(CN) C03 Vhys() Differential Input Hysteresis TTL = 0, LVDS = 1 Vhys() = Vth()hi-Vth()lo (guaranteed by design)
0.8 0.8 -200
3 1.5 200
V V mV
1.2
8
mV
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
OPERATING REQUIREMENTS: SPI Interface
Operating Conditions: VDD = 3 . . . 5.5 V, Tj = -40 . . . 125 C, unless otherwise noted. Item No. Symbol Parameter Conditions Min. Setup Time: NCS hi lo before SCK lo hi Setup Time: MOSI stable before SCK lo hi Hold Time: MOSI stable after SCK lo hi Signal Duration SCK hi Signal Duration SCK lo Hold Time: NCS lo after SCK lo hi Signal Duration NCS hi Propagation Delay: MISO stable after SCK hi lo Propagation Delay: MISO high impedance after NCS lo hi Clock Frequency 15 20 0 25 25 25 0 40 25 Max. ns ns ns ns ns ns ns ns ns Unit
SPI Interface I001 tsCCL I002 tsDCL I003 thDCL I004 tCLh I005 tCLI I006 thCLC I007 tCSh I008 tpCLD I009 tpCSD
I010 f(SCK)
10
MHz
tCSh
NCS
tsCCL
SCK
tCLh tsDCL thDCL
tpCLl
thCLC
MOSI
MSB in tristate
LSB in
MISO
tCSh
NCS
tpCLh tpCLl
SCK
thCLC
MOSI
don't care
tpCLD
MISO MSB out
tpCLD
LSB out
tpCSD
Figure 1: SPI write cycle (top) and read cycle (bottom)
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
CONFIGURATION PARAMETERS Read/Write Registers Read-Only Registers
Configuration INVZ(1:0) EXCH(2:0) CNTCFG(2:0) TTL CBZ(1:0) CFGZ(1:0) TPCFG(1:0) PRIOR MASK(9:0) NMASK(1:0) LVDS CH2SEL ENCH2 CH1SEL ENCH1 CH0SEL NENCH0
invert Z signal exchange inputs AB counter configuration TTL/differential inputs clear counter by zero zero signal configuration TPI configuration SPI/BiSS communication priority error/warning mask error/warning not mask LVDS/RS-422 differential inputs BiSS channel 2 select BiSS channel 2 enable BiSS channel 1 select BiSS channel 1 enable BiSS channel 0 select BiSS channel 0 not enable
Status AB NERR NWARN TP1 NTPVAL NABERR TP2 REF UPD NUPDVAL
counter values error bit (low active) warning bit (low active) touch-probe 1 register touch-probe valid (low active) AB counter error (low active) touch-probe 2 register reference register update register update register valid (low active) Table 7: Counter Registers
Error ABERRx AB signals error in counter x EXTERR external error Table 8: Error Registers
Table 5: Register description Write-Only Registers Warning OVFx ZEROx PDWN RVAL UPDVAL OVFREF TPVAL EXTWARN COMCOL TPS ENSSI overflow in counter x signals zero value in counter x power-down reset REF value valid update register up to date overflow in REF counter new touch-probe value available external warning communication collision actual TPI pin status SSI enabled Table 9: Warning Registers
Instructions ACT1 set value of ACT1 pin ACT0 set value of ACT0 pin TP latch TP1 and TP2 ZCEN enable zero codification ABRES2 reset AB counter 2 ABRES1 reset AB counter 1 ABRES0 reset AB counter 0 Table 6: Instruction Byte
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
REGISTER MAP
PROGRAMMING Adr
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 TE SE IDDQ CLK2ACT1 SSIGRAY IVA LVDS CH2SEL ENCH2 CH1SEL ENCH1 TTL
Bit 7
Bit 6
INVZ(1:0) CBZ(1:0)
Bit 5
Bit 4
EXCH(2:0)
Bit 3
Bit 2
Bit 1
CNTCFG(2:0)
Bit 0
Configuration
CFGZ(1:0) MASK(7:0) NMASK(1:0) CH0SEL NENCH0 MASK(9:8) TPCFG(1:0) PRIOR
Measurement Data (SPI read only)
0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E TP2(23:0) + NTPVAL + NABERR TP1(23:0) + NTPVAL + NABERR UPD(23:0) + NUPDVAL + NABERR AB/SPICH(47:0) + NWARN + NERR
Measurement Data (SPI and BiSS read only)
0x10 0x11 0x12 REF(23:16) REF(15:8) REF(7:0)
SPI write only data. (read via AB)
0x20 0x21 0x22 0x23 0x24 0x25 SPICH(47:40) SPICH(39:32) SPICH(31:24) SPICH(23:16) SPICH(15:8) SPICH(7:0)
Instruction Byte (write only)
0x30 ACT1 ACT0 TP ZCEN ABRES2 ABRES1 ABRES0
BiSS Profile ROM
0x42 0x43 BiSS Profile ROM - 0x33 BiSS Profile ROM - 0x18
Status
0x48 0x49 0x4A ABERR0 ABERR1 ABERR2 OVF0 OVF1 OVF2 ZERO0 ZERO1 ZERO2 PDWN PDWN PDWN RVAL EXTERR EXTERR UPDVAL EXTWARN EXTWARN OVFREF COMCOL COMCOL TPVAL TPS ENSSI
BiSS Device and Manufacturer ID
0x78 0x79 0x7A 0x7B 0x7C Device ID - 0x4D ('M') Device ID - 0x44 ('D') Revision - 0x59 ('Y') Revision - 0x00 ('0') Revision - 0x00 (")
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
PROGRAMMING Adr
0x7D 0x7E 0x7F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision - 0x00 (") BiSS Manufacturer ID (default 0x69) BiSS Manufacturer ID (default 0x43)
Table 10: Register layout
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
RS-422, LVDS, TTL RECEIVERS The input stage for the incremental signals ABZ is configurable as single-ended TTL and differential (RS-422 or LVDS). Differential inputs are possible only for one counter configuration. If two or more counters are configured, it must be used one of the TTL inputs configuration shown in table 11. Counters 1xTTL 2xTTL 3xTTL A0 AP AP AP B0 Z0 A1 B1 Z1 A2 B2 AN BP AN BP BN CP CN AN - BP BN - CP CN
LVDS Code 0 1 Notes Addr. 0x03; bit (7) Function differential RS-422 inputs differential LVDS inputs condition: TTL=0 0
Table 13: LVDS/RS-422 Inputs The configuration bit EXCH exchanges the input A and the input B of the counters. The default counting direction is positive in clockwise (CW) direction (A edge take place before B edge). But it is also possible to change the counting direction with the register EXCH. See table 14.
EXCH Code xx1 x1x 1xx Addr. 0x00; bit (5:3) Function exchange AB CNT0 (CCW positive) exchange AB CNT1 (CCW positive) exchange AB CNT2 (CCW positive) 000
Table 11: TTL Input Counters Configuration
Note that the three counters configuration don't implement any Zero signal. It has only A and B input signals. Register bits TTL and LVDS set the configuration of the quadrature input signals.
TTL Code 0 1 Addr. 0x01; bit (7) Function differential inputs TTL inputs 0
Table 14: Exchange AB Inputs The index (Z) signal can be inverted as shown in table 15 with the register bits INVZ(1:0).
INVZ Code x1 1x Addr. 0x00; bit (7:6) Function invert Z CNT0 (Z=0 active) invert Z CNT1 (Z=0 active) 00
Table 12: TTL Inputs
It is possible to configure the differential input stage of iC-MD in two different modes; differential RS-422 and differential LVDS. See table 13.
Table 15: Invert Z Signal
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
48 BIT COUNTER iC-MD has a 48 bit counter configurable as from one up to three counters with bit lengths from 16 to 48 bit. Table 16 shows all the possible counters configuration. The counter configuration is given by the registers CNTCFG as shown in table 16. If it is configured with more than one counter, the input stage must be set to TTL (table 12).
CNTCFG Code 000 001 010 100 101 011 110 111 Addr. 0x00; bit (2:0) Counter Configuration 1x24 bit counter 2x24 bit counter 1x48 bit counter 1x32 bit counter 1x32 bit + 1x16 bit counter 1x16 bit counter 2x16 bit counter 3x16 bit counter 000
EXCH = 0 and INVZ = 0. All other configurations are also possible.
CFGZ Code 00 01 10 11 Addr. 0x01; bit (4:3) Function: Z active: when A = 1 B = 1 Z active: when A = 1 B = 0 Z active: when A = 0 B = 1 Z active: when A = 0 B = 0 00
Table 17: Index Signal Configuration It can also be deactivated the clearing of counter by the index signal with the configuration bit CBZ ( table 18 ). The CBZ configuration is only applicable after the second index pulse after power-on or the activation of ZCEN (table 23), because after it, the iC-MD will reset the counter value by the firsts two index pulse, independently of the CBZ configuration, in order to have the AB Counter value referenced to the second index pulse. By default, CBZ is set to 0, also the counters are not reset to 0 by the index signal. But the firsts two Index pulse always reset the counters.
CBZ Code x1 1x Addr. 0x01; bit (6:5) Function CNT0 cleared by Z0 signal CNT1 cleared by Z1 signal 00
Table 16: Counter Length The 48 bit register of the AB counter is also used as "SPI data channel" for data exchanging between SPI and BiSS interface, for that purpose the bit CH0SEL (table 45) must be set to 1. When CH0SEL = 1, the counting function for all the counters is deactivated.
Index Signal (Z) In default operation configuration, the index signal (Z) is active when A = B = 1, as shown in table 17 with
Table 18: Clear by Z
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
24 BIT REFERENCE COUNTER An aditional 24 bit counter is integrated in order to load the REF and UPD registers. The value of this internal counter can not be read, it can only be read the values of REF and UPD registers. The reference counter is activated by default after power-on and reset with every index signal (it is not affected by the configuration bit CFGZ, table 17). Since the internal counter for REF and UPD is 24 bit long, the maximum number of edges that can be evaluated (loaded in UPD and REF) between two index signal goes from -223 (negative counting direction) to 223 -1 (positive counting direction).
REF REGISTER After the start up (Power on), the iC-MD counts the number of edges between the first two different index signals (Z) in the register REF. This function is always activated by the following situations: - after power-on. - by activating the zero codification function via instruction byte (table 23). The process runs as following: the "reference counter" is set to zero with the first index signal, and the second index signal (must be different of the first one) loads the register REF with the value of "reference counter". It is the distance between the first and the second index signals. The AB counter is then set to 0 with the second index signal. The counter value is then referenced to the position of the second Z signal, and the number of edges between the first two index signals stored in REF. After the second index signal, the status bit RVAL (table 31) is set and remains at this value until the next power on, the activation of the zero codification function or until the reseting of the counter 0. The following diagrams show the reference position acquisition process also called as zero codification function.
Figure 2: Zero-Codification: REF and UPD registers after activation of Zero Codification function
Figure 3: Zero-Codification: reference position acquisition
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
UPD REGISTER The register UPD is load at every index pulse with the value of the "reference counter", it is the number of AB edges between the last two index pulses (value of the reference counter). It is used to check that any AB pulse was lost. The status bit UPDVAL (table 32) signals that a new UPD value is available (UPD register was loaded and still not read). The following diagram shows the value of REF and UPD after activating the zero codification function when counting in negative direction.
5000 5005 5005
5000 5005
5000
Z
Bit ZCEN=1
2510
Z
2490
Z
2515
Z
2485 Z Negative counting direction
2520
Z
2480
Z
2525
Z
REF UPD CNT
0 X X
-2510 -2510 0+n
-2510 -2490 -2490+n
-2510 -2515 -2515+n
-2510 -2485 -5000+n
-2510 -2520 -5520+n
-2510 -2480 -10000+n
Figure 4: REF and UPD registers in negative direction
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
TP1, TP2 and AB REGISTERS TP1, TP2 Registers The touch probe registers consist of two 24 bit registers which are load with a TPI pin event (see table 19) or writing the instruction bit TP (table 24) via SPI/BiSS. At every TPI pin or TP instruction event, the register TP2 is load with the value of TP1 and TP1 is load with the actual value of counter 0. For using TP registers, AB counter must be configured to 24 bit, but if 2x24 bit counters are configured, only the counter 0 will be latched into TP1/TP2 registers. The TPI pin events can be configured as falling, rising or both edges, as shown in table 19.
TPCFG Code 00 01 10 11 Addr. 0x01; bit (2:1) Function both edges active rising edge active falling edge active pin TPI disabled 00
Table 19: TPI Pin Configuration The following diagram (figure 5) shows the function of the pin TPI when configured for both rising and falling edge.
Figure 5: Function of TPI pin when TPCFG=11 AB Register A 48 bit register (AB) is used to store and shift out the ABCNT Registers (Counters), and also the "SPI Channel Data" (SPICH). The register AB is read via BiSS (sensor data, channel 0) or via SPI (Adr 0x08), and the bit length is set by the configuration bits CNTCFG (table 16) The bit CH0SEL (table 45) selects the data to be load in the AB register when reading the channel 0 via BiSS or the address 0x08 via SPI.
iC-MD RS-422 QUADRATURE
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
COMMUNICATION CONTROL iC-MD can communicate simultaneously via SPI and BiSS in order to exchange data between SPI and BiSS. For this purpose, SPI writes the data to be read by BiSS in the AB register, and BiSS reads the SPICH (BiSS channel 0 configured as SPICH, see table 45).
ABRES2 Code 1 Addr. 0x30; bit 2 Function reset of counter 2 0
Table 22: Counter 2 Reset
ZCEN Code 1 Addr. 0x30; bit 3 Function enable zero codification 1
If both interfaces attempt to read or write at the same time a different RAM address than the SPICH (Adr. 0x20 to 0x25), then the bit error COMCOL (table 37) is set and the communication of the interface without priority (see table 43) is not valid.
Table 23: Enable Zero Codification
TP Code 1 Notes Addr. 0x30; bit 4 Function load TP2 with TP1 value, and TP1 with ABCNT value counter must be configured to 24 bit length -
Instruction Byte
Register address 0x30 contains the write only instruction byte. When one of these bits is set to 1, then the corresponding operation is executed and then set back to 0, excepts the bits ACT0 and ACT1 which remain to the written value.
Table 24: Touch Probe Instruction The instruction bits ACT0 and ACT1 set the actuator pins ACT0 and ACT1 to high or low voltage.
ACT0 Code 0 1 Addr. 0x30; bit 5 Function actuator pin 0 set to GND actuator pin 0 set to VDD 0
ABRES0 Code 1
Addr. 0x30; bit 0 Function reset of counter 0
0
Table 20: Counter 0 Reset
ACT1 Code 0 1
Table 25: Actuator Pin 0
Addr. 0x30; bit 6 Function actuator pin 1 set to GND actuator pin 1 set to VDD 0
ABRES1 Code 1
Addr. 0x30; bit 1 Function reset of counter 1
0
Table 21: Counter 1 Reset
Table 26: Actuator Pin 1
STATUS REGISTER and ERROR/WARNING INDICATION The three bytes status registers (Adr. 0x48 to 0x4A) indicate the state of the iC-MD. All the status bits are latched (except TPS) when an error/warning occurs and are reset when reading the error/warning via SPI or BiSS excepts RVAL. The status bits TPVAL and UPDVAL are also reset by reading the register TP1 and UPD respectively. Two of this status bits are error bits; ABERR (AB decodification error, table 27) and EXTERR (external error, table 35), all others status bits signal warnings.
The status bit TPS (table 38) is not latched, it signals the actual state of the input pin TPI.
Status bits ABERRx indicate a decodification error of the AB inputs, it ocurrs if the counting frequency is too high or if two incremental edges are too close (PHab2, Spec. Item No.303).
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ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
ABERRx Code 0 1 Notes
Addr. 0x48, 0x49, 0x4A; bit 7 Description No decodification error in counter x Decodification error in counter x x = 0, 1, 2 Reset by reading Adr. 0x48 (ABERR0), 0x49 (ABERR1) and 0x4A (ABERR2) The corresponding counter must be reset (ABRES) after an error
RVAL status bit indicates that the reference value was load in the REF register, after the "Zero Codification" process. After power-on, this bit remains at 0 until the second different Index pulse.
RVAL Code 0 1 Notes Addr. 0x48; bit 3 Description REF Reg. not valid REF Reg. valid Reset by the instruction ZCEN(see table 23)
Table 27: AB Decodification Error Table 31: REF Register Valid The maximum counting range of the counters depends on the counter configuration (see table 16). A counter with the bit length "n" has the maximum counting range will be from -2n-1 up to 2n-1 -1. The corresponding bit OVFx is set to 1 if the counter exceeds these values.
OVFx Code 0 1 Notes Addr. 0x48, 0x49, 0x4A; bit 6 Description no overflow in counter x overflow in counter x x = 0, 1, 2 reset by reading Adr. 0x48 (OVF0), 0x49 (OVF1) and 0x4A (OVF2)
Every time that the UPD register is loaded, the status bit UPDVAL (UPD valid) is set to 1 until the status bit UPD or the register UPD is read via SPI or BiSS.
UPDVAL Code 0 1 Notes Addr. 0x48; bit 2 Description UPD Reg. not valid UPD Reg. valid Reset by reading Adr. 0x48 or the register UPD via SPI (Adr. 0x0A) or BiSS (Channel 1)
Table 32: UPD Register Valid If the number of AB edges between two index signals is greater than 223 -1=8388607 or lower than -223 =8388608 the status bit OVFREF is set to 1 and indicates that the value of the UPD and REF registers are not valid.
OVFREF Code 0 1 Notes Addr. 0x48; bit 1 Description No Overflow in reference counter Overflow in reference counter Reset by reading Adr. 0x48
Table 28: Counter Overflow Warning ZEROx bits indicate that the counter value has reached the zero value.
ZEROx Code 0 1 Notes Addr. 0x48, 0x49, 0x4A; bit 5 Description no zero of counter x zero of counter x x = 0, 1, 2 reset by reading Adr. 0x48 (ZERO0), 0x49 (ZERO1) and 0x4A (ZERO2)
Table 33: Reference Counter Overflow Table 29: Zero Value in Counter x If VDD reaches the power off supply level (VDDoff, Spec. Item No. 602), the iC-MD is reset and the RAM initialized to the default value. Status bit PDWN indicates that this initialization has taken place.
PDWN Code 0 1 Notes Addr. 0x48, 0x49, 0x4A; bit 4 Description No undervoltage Undervoltage Reset by reading Adr. 0x48, 0x49 or 0x4A
After loading TP1/TP2 register, either via pin TPI or instruction TP (see table 24), the bit TPVAL is set to 1 and remains at 1 until the reading of TPVAL, TP1 or TP2 via SPI or BiSS.
TPVAL Code 0 1 Notes Addr. 0x48; bit 0 Description TPx registers not loaded New value loaded in TPx Reset by reading Adr. 0x48, register TP1 or register TP2 via SPI (Adr. 0x0C and 0x0E) or BiSS (channel 1 and channel 2, see table 45)
Table 30: Undervoltage Reset
Table 34: Touch-Probe Valid
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The status bit (EXTERR: external error) indicates if the pin NERR was either pulled-down from outside or set to 0 from inside (an internal masked error has ocurred).
EXTERR Code 0 1 Notes Addr. 0x49, 0x4A; bit 3 Description no external error external error Reset by reading Adr. 0x49 or 0x4A
TPS Code 0 1
Addr. 0x49; bit 0 Description TPI pin at low TPI pin at high
Table 38: Touch-Probe Pin Status Status bit ENSSI signals if the SSI interface instead of BiSS is configured. This is configured by the SLI pin, if the pin is open, the SSI interface is selected. ENSSI has an internal digital filter of 12.5 s.
ENSSI Code 0 1 Addr. 0x4A; bit 0 Description SSI not enabled SSI enabled (pin SLI open)
Table 35: External Error
The status bit (EXTWARN: external warning) bit indicates if the pin NWARN was either pulled-down from outside or set to 0 from inside (an internal masked warning has ocurred).
EXTWARN Code 0 1 Notes Addr. 0x49, 0x4A; bit 2 Description no external warning external warning reset by reading Adr. 0x49 or 0x4A
Table 39: Enable SSI Error and warning mask
Table 36: External Warning
The masks (MASK) and not masks (NMASK) bits, stipulate whether error and warning events are signaled as an alarm via the open drain I/O pins NERR and NWARN.
MASK Bit 9 8 7 6 5* 4 3 2 1 0 Notes Adr 0x02, bit 7:0; Adr 0x03, bit 1:0 Error/Warning Event enable SSI (warning) external error (error) zero value of active counter 0, 1 or 2 (warning) touch-probe valid (warning) power down (RAM was initialized) (warning) overflow of reference counter (warning) overflow of counter 0, 1 or 2 (warning) REF reg. valid (warning) external warning (warning) register comunication collision (warning) encoding of bit 9 . . . 0: 0 = message disabled, 1 = message enabled
If BiSS/SSI and SPI try to access at the same time to the internal data bus (BiSS register communication and SPI communication) the bit COMCOL will be set indicating that a collision has taken place. If SPICH is activated (table 45), the writing process of AB via SPI and reading of channel 0 via BiSS at the same time will generates no COMCOL warning. If a communication collision take place, only the interface with priority (See table 43) executes the write/read process correctly, but the other interface doesn't write any data or read a false value.
COMCOL Code 0 1 Notes Addr. 0x49, 0x4A; bit 1 Description no communication collision communication collision reset by reading Adr. 0x49 or 0x4A
Table 40: Error/Warning Event Masks
NMASK Bit 1 Adr 0x03, bit 3:2 error/warning event AB decodification error. e.g. too high frequency(error) UPD reg. valid (warning) encoding of bit 1...0: 0 = message enabled, 1 = message disabled
Table 37: Communication Collision
0 Notes
Bit TPS signals the actual state of the input pin TPI. If the pin TPI is high, the bit TPS remains at 1, and if TPI is set to low, TPS status bit is 0.
Table 41: Error/Warning Event Not Masks
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SPI INTERFACE The Serial Peripheral Interface (SPI) of iC-MD consists of a SPI slave interface with polarity 0 and phase 0. Each transmission starts with a falling edge of NCS and ends with the rising edge. During transmission, commands and data are controlled by SCK and NCS according to the following rules: * Commands and data are shifted; MSB first, LSB last * Each output data/status bits are shifted out on the falling edge of SCK (MISO line) and each bit is sampled on the rising edge of SCK (Polarity 0, Phase 0). * After the device is selected with the falling edge of NCS, an 8-bit command is received. The command defines the operations to be performed (Write/Read) and the address. * The rising edge of NCS ends all data transfer and resets internal counter and command register * Data transfer out from MISO starts with the falling edge of SCK immediately after the last bit of the SPI command is sampled in on the rising edge of SCK * Data transfer to MOSI continues immediately after receiving the command in all cases where data is to be written to iC-MD internal registers
SPI Communication The first byte to be transmitted to the iC-MD via SPI is the instruction (or command) wich determine the communication direction (read or write), and has the following structure:
Bit 7 R/W
Bit 6
Bit 5
SPI Commands Bit 4 Bit 3 Bit 2 ADDRESS(6:0) Table 42: SPI command structure
Bit 1
Bit 0
The following diagrams show the SPI write and read processes.
NCS SCLK MOSI MISO
0 ADR(6:0) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
Polarity 0, Phase 0
Byte to write in ADR
Byte to write in ADR+1
High Impedance
Figure 6: SPI Write Data
NCS SCLK MOSI MISO
1 ADDRESS(6:0)
Polarity 0, Phase 0
don't care
High Impedance
n
n-1
n-2
n-3
n-4
n-5
5
4
3
2
1
0
X
High Impedance
Figure 7: SPI Read Data The data length to be written is always 8 bit, but it is possible to transmit several bytes of data consecutively if the NCS signal is not reset and SCLK continues being clocked. The address transmitted is then the start
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address which is internally increased by 1 following each transmitted byte. The data length to be read after the read instruction is variable: 8 bit For configuration data (Adr.- 0x00 to 0x07), REF and SPICH (Adr.- 0x10 to 0x25), ROM (Adr.- 0x42, 0x43) and Status Bit (Adr.- 0x48 to 0x4A). But it is possible to read several bytes of data consecutively if the NCS signal is not reset and SCLK continues being clocked. The address transmitted is then the start address which is internally increased by 1 following each transmitted byte. 24+2 bit For TP1, TP2 and UPD registers. Variable For counter data, it depends on the counter configuration CNTCFG (Adr. 0x00 bit (2:0)). See the table 16. The total length is CNT length + 2 bit (NERR, NWARN) Interface Priority The Configuration bit PRIOR (Adr. 0x03, bit 1), set which interface has priority when taking place a Read/Write interface collision. It means that if BiSS and SPI try to access to the configuration register at the same time, then only the one with the priority will write/read
succefully the register. The error in the interface without priority will be signalized by the collision Status bit: SPICOL or BISSCOL, Adr.0x4A, bit(1:0).
PRIOR Code 0 1 Addr. 0x03; bit 1 Function BiSS priority SPI priority 0
Table 43: Interface Priority SPI Channel: SPI to BiSS communication The counter register is also used for the transmission of data from SPI to BiSS. The data exchanging take place as following: 1. SPI writes the data to be transmitted in address 0x20 to 0x25, this data is written in the counter registers. The data lenght to be transmitted is selected by CNTCFG (Table 16) and can be configured as 16, 24, 32 or 48-bit 2. After the writing process, the bit SPICHVAL is set to 1 and read via BiSS as Warning bit of channel 0. 3. BiSS reads out the channel 0, the data written via SPI and two status bits, NERR and NWARN wich indicates if the read data is valid.
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BiSS and SSI INTERFACE The BiSS interface is a bidirectional serial interface, which is used to read out the sensor data values and to write and read the internal configuration registers. For a detailed description of the protocol, see the BiSS C specification. It consist of 3 configurable channels:
channel CH0
CH1 CH2 Notes
data length CRC polynom CRC mode 16 + 2 bit 1000011 inverted 24 + 2 bit 32 + 2 bit 48 + 2 bit SPI Channel NERR NSPICHVAL 16 + 2 bit 1000011 inverted 24 + 2 bit 32 + 2 bit 48 + 2 bit UPD NABERR NUPDVAL 24 + 2 bit 100101 inverted TP1 NABERR NTPVAL 24 + 2 bit 100101 inverted TP1 NABERR NTPVAL 24 + 2 bit 100101 inverted TP2 NABERR NTPVAL 24 + 2 bit 100101 inverted channel 0 data length configurable via: CNTCFG (Adr.0x00, bit 3:0) Table 44: BiSS Channels
eata AB counter
error NERR
warning NWARN
The error (NERR) and warning (NWARN) bit of the channel 0 signal the same data to be output at the pins NERR and NWARN, it's by default: NERR: ABERR (AB signal error) NWARN: UPDVAL (UPD Reg. up to date) This bits can also be configured like the NERR and NWARN outputs, with the registers MASK (table 40) and NMASK(table 41) Two different data can be selected for each channel, register CHxSEL (table 45) selects the data to be transmitted by the channels.
CHxSEL Code XX0 XX1 X0X X1X 0XX 1XX Addr. 0x04; bit (7,5,3) Function channel 0: channel 0: channel 1: channel 1: channel 2: AB counter data SPI data channel UPD data TP1 data TP1 data 000
The three channel are enabled by default, but all of them can be disable with the registers NENCH0 (table 46) and ENCHx (table 47)
NENCH0 Code 0 1 Addr. 0x04; bit (2) Function BiSS channel 0 enabled BiSS channel 0 disabled 0
Table 46: Not Enable BiSS Channel 0
ENCHx Code X0 0X Addr. 0x04; bit (6,4) Function BiSS channel 1 disabled BiSS channel 2 disabled 00
Table 47: Enable BiSS Channel 1 and 2 SSI Protocol An SSI protocol is selected if the input pin SLI is open. This enable signal has an internal digital filter of 5 s. A clock pulse train from a controller is used to gate out sensor data. Between each clock pulse train there is a SSI timeout during which fresh data is moved into the register. Data is shifted out when the iC-MD receives a pulse train from the controller. When the least sig-
channel 2: TP2 data
Table 45: BiSS Channel Selection
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nificant bit (LSB) goes high after the SSI timeout, new data is available to read. The AB counter data transmitted is in the form of a binary code (24 bit + NERR + NWARN). If the input MA
continues being clocked without SSI timeout, it will be output a total of 94 bit with the following scheme:
Figure 8: Output data with SSI protocol
ACTUATOR OUTPUTS, ERROR and WARNING I/O PINS The pins NERR and NWARN are low active bidirectional ports (open collector outputs and digital inputs). The inputs are used to latch an external error/warning (tables 35 and 36) and makes possible that this error/warning will be read by the controller via SPI or BiSS as status bits. The instruction bits ACT0 and ACT1 (tables 25 and 26) set the value of the output pins ACT0 and ACT1.
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APPLICATIONS NOTES RS422 12 V capable inputs setup
The following figure shows the resistors configuration used for a 12 V capable RS422 inputs. (see Fig. 9).
VDD 0..5.5V
VDD
RS-422 Receivers
R R
1k
1k
AP
AP
AP
A0 B0
24-bit REF Counter
Z Signal COUNT Reset REFCNT(23:0) RESAB
APR ANR -12..12V -12..12V
4.7k
R R
+
R R
AD
Z0
4.7k
1k
1k
AN
1k 1k
AN AN BP
R
BPR BNR -12..12V -12..12V
4.7k
R R
R
BP
BP
+
R R
BD
4.7k
1k
1k
BN
1k 1k
BN BN A1 B1 CP CP Z1
1x48bit Counter 1x32bit Counter 1,2x24bit Counters 1,2,3x16bit Counters
Z CBZ & AB(47:0)
R
CPR CNR -12..12V -12..12V
4.7k
R R
R
CP
+
R R
1 CD A2 B2 CN
DQ
4.7k
1k
1k
CN
CN
CNTFLG
TPI
Figure 9: RS422 12 V capable configuration
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying - even as an excerpt - is only permitted with iC-Haus' approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
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ORDERING INFORMATION
Type iC-MD Evaluation Board iC-MD
Package TSSOP20 100 mm x 80 mm PCB
Order Designation iC-MD TSSOP20 iC-MD EVAL MD1D
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners

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